IBM kündigt zwei technologische Durchbrüche im Nanobereich an

In der Industrie liegt die Aufmerksamkeit bei der Nanotechnologie überwiegend auf ausgefallenen und „futuristischen“ Beispielen. IBM kündigt heute zwei technologische Durchbrüche an, die eine praktische Anwendung dieser Technologie zeigen. Mehr Details präsentiert IBM in der kommenden Woche auf der IEDM (International Electron Devices Meeting) in San Francisco:

IBM stellt die weltweit kleinste SRAM-Speicherzelle vor, deren Größe bis zu sieben Mal kleiner ist als bislang erhältliche Speicherzellen. Die neue SRAM-Zelle reduziert den Platz für den Speicher auf einem Chip, so dass mehr Speicherkapazität auf der Chip-Fläche zur Verfügung steht oder die Chip-Größe sich verringern lässt. Über 50.000 dieser Speicherzellen lassen sich auf der Fläche von der Größe eines menschlichen Haarendes unterbringen.

IBM kündigt eine Technik an, die die Leistung von Transistoren in Halbleitern verdreifacht. Mit Hilfe eines Prozesses, der zur konventionellen CMOS-Technologie kompatibel ist, lässt sich die Leistung von Chips und deren elektronischen Systemen deutlich steigern. Die Technik nutzt eine zusätzliche Lage des Elements Germanium im kritischen Bereich des Transistors, in dem die elektrischen Ströme fliessen (Channel). Der Einsatz dieses „Strained Germaniums“ könnte zukünftig helfen, die Leistung von Chips im 32 Nanometer-Bereich und kleiner zu verbessern .

Weitere Informationen finden Sie in den englischen Original-Meldungen:

IBM unveils world´s smallest SRAM Memory Cell

Yorktown Heights, N.Y., December 6, 2004. . . IBM today announced it has built a critical component for a high-speed computer memory that is about ten times smaller than those currently available, potentially enabling a major system performance boost for critical business applications.

Called a static random access memory (SRAM), this form of memory is needed in greater and greater quantities on computer processor chips to enable the higher system performance required for demanding applications like banking and digital media. Yet, the space available for SRAM on these chips is limited by cost and manufacturing limitations, presenting a significant technical challenge. IBM has demonstrated that the SRAM memory can be made significantly smaller and still operate properly, thereby allowing more to be included on each chip.

Traditionally, SRAM is made more dense by shrinking its basic building block, often referred to as a cell. The new IBM SRAM cell is less than half the size of the smallest experimental cell reported to date, and seven times smaller than those available today. To put this in perspective, about 50,000 of the IBM cells could fit on the circular end of a single human hair. This breakthrough demonstrates the possibility of continued system performance improvement for three additional technology generations beyond what is currently manufactured. The technology is being unveiled in December at the 2004 International Electron Devices Meeting (IEDM) in San Francisco.

“Our continued commitment to technology leadership is driven by the needs of our customers,” said Dr. T.C. Chen, vice president of Science and Technology, IBM Research. “Our ability to create critical electronic components at these small scales ultimately means our systems will be able to tackle harder problems. We develop the technology and our server systems are the vehicles that put this technology to work in powerful ways.”

IBM researchers optimized the SRAM cell design and circuit layout to improve stability and developed several novel fabrication processes in order to make the new SRAM cell possible. The key element was IBM’s utilization of mixed electron-beam and optical lithography to print the aggressive pattern dimensions and densities. SRAM cell size is a key technology metric in the semiconductor industry, and this work demonstrates IBM’s continued leadership in cutting-edge process technology.

The SRAM size achieved by IBM could enable gigabits of on-chip memory with ten times higher capacity than the current state-of-the-art technologies. This innovative technology could pave the way for new applications, such as faster search processing, and enable the growth of on demand computational capabilities for IBM customers.

IBM demonstrates Technique for extending Chip Performance

Yorktown Heights, N.Y., December 6, 2004. . . IBM today announced it has demonstrated a technique that triples the performance of a standard transistor used in semiconductors by a process that is compatible with conventional CMOS technology, a major step toward achieving continued performance enhancement of chips and the electronic systems that use them.

The technique involves the creation of a layer of the element germanium in the critical portion of the transistor through which electrical current flows, called the “channel.” Germanium has long been known to have better conductivity than silicon, and the strain in the germanium layer created by IBM’s process leads to even further performance gains.

The semiconductor industry has recently embraced the concept of enhancing circuit performance by boosting the transistors’s current transport properties–known as mobility. One such example is the introduction of strained silicon, which is in production by several companies today. Strained germanium has been shown to have significantly better transport properties than silicon or strained silicon. However, until now there has not been a path to enable the combination of strained germanium with conventional circuit fabrication techniques. IBM has demonstrated methods that can selectively place the strained germanium on the selected areas of a chip using a CMOS-compatible process.

The introduction of a new material like germanium in the critical areas of the integrated circuits provides an alternative means of improving chip performance from the traditional method of simply shrinking circuitry. This is becoming increasingly important as further miniaturization becomes more difficult and yields diminishing returns. IBM believes this new technique could help ensure continued performance improvements in chips with circuit sizes of 32 nanometers (nm) and smaller.

“System performance depends on chip performance, and that will increasingly depend on new materials and design techniques rather than simple scaling,” said T.C. Chen, IBM Fellow and vice president of Science and Technology, IBM Research. “With this work we’ve drawn from our experience introducing technologies like silicon germanium, silicon-on-insulator and strained silicon. Our focus is on the application of that learning to develop innovative solutions for our customers.”

The introduction of new materials in semiconductors can have profound effects, often creating new problems in other areas or demanding radically different manufacturing processes. What is unique about IBM’s results is that the selective introduction of strained germanium only in the critical areas of the integrated circuit provides a transistor with three times the performance without affecting other devices or circuits on the same chip. This dramatically reduces the risk of introducing a new material..

Within the transistor itself, IBM’s selective strained-germanium technique actually introduces other fringe benefits. For example, the IC industry is looking for solutions to replace conventional SiO2 gate oxide using “high-K” insulators. However, introducing a new “high-K” insulator material to the existing silicon technology is found to be especially challenging; the electrical properties of the strained germanium actually provides an easier path for the introduction of “high-K” insulators.

IBM will present the findings from this work in more detail at the upcoming International Electron Devices Meeting (IEDM) in San Francisco.